SUNNYVALE, Calif. - November 8, 2004 - Today Spansion LLC, the Flash memory subsidiary of AMD (NYSE:AMD) and Fujitsu Limited (TSE:6702), laid out an ambitious three-year vision and strategic road map, outlining plans to scale its MirrorBit(tm) technology to 8?gigabit densities on 65-nanometer lithography to meet the growing demands of the entire Flash market - from wireless handsets and embedded systems to detachable cards and USB drives. In addition, the company announced plans to develop a new "ORNAND" Flash memory architecture that brings together the best of NOR code execution and NAND data storage capabilities in a single product based on MirrorBit technology.

"MirrorBit technology is Spansion's competitive weapon and affords us the versatility to serve the entire Flash memory market," said Dr. Bertrand Cambou, president and CEO of Spansion. "Our upcoming MirrorBit products are designed to transcend the NOR versus NAND debate and provide our customers with optimal solutions for both code and data storage. With innovations such as Spansion's ORNAND architecture, we can enable our customers to create highly differentiated systems or even invent entirely new product categories."

Spansion's newly announced product road map is expected to extend the reach of MirrorBit technology to encompass the complete range of densities, performance, cost and reliability required by the overall Flash memory market. Spansion plans to sample the industry's first 90?nanometer 1?gigabit NOR device and new mass data storage products for mobile phones[1] in early 2005. With further scaling to 8-gigabits by 2007, the company's MirrorBit product line is expected to eventually include the complete range of densities and solutions required by Spansion customers.

"Now that Spansion has been able to solve some of the inherent scaling and performance problems with nitride-based technology, its new 'ORNAND' architecture is truly a breakthrough," said Alan Niebel, CEO and founder of semiconductor market analysis firm Web-Feet Research. "Being able to add additional features and performance to high-density Flash while reducing cost will help secure Spansion's success in the removable data storage market. Today, the Flash memory market is roughly divided between NOR and NAND technology. Spansion's strategy to create a new ORNAND architecture that transcends traditional boundaries of memory and storage presents an opportunity for customers to significantly extend the capabilities of next generation of digital devices."

The first of Spansion's new ORNAND products is expected to become available in 2005 with burst-write speeds up to four times faster than current NAND products, and all the inherent benefits of MirrorBit NOR technology, including high reliability, fast read speeds and low cost. By 2007, Spansion plans to offer a full portfolio of ORNAND products scaling to 8-gigabit densities. As a result, Spansion expects MirrorBit technology to serve the anticipated $8.9 billion per year data storage market[2] previously served primarily by floating-gate NAND-type products.

MirrorBit technology is ideally suited for new applications beyond traditional memory as well. Because MirrorBit process technology is logic-friendly, Spansion can integrate blocks of logic within high-density arrays of Flash memory. This fundamental capability enables Spansion to create new types of memory solutions, based on the ORNAND architecture, that incorporate logic functions like high-security cryptographic processors or integrated memory controllers, to bring more value to customers.

Spansion's award-winning MirrorBit technology is a comparatively simple but powerful approach to Flash memory, with the unique ability to store two or more bits of data in a single Flash memory cell. The company has also demonstrated MirrorBit technology's ability to quadruple densities with a working proof-of-concept "QuadBit" test chip in its state-of-the-art Submicron Development Center. In addition, Spansion has a working test chip prototype based on 65?nanometer MirrorBit technology, proving the technology's scalability to smaller process geometries.