Review: AMD 760MPX Chipset Overview

Introduction

As a precursor to our upcoming MSI K7D Master review we thought it would be a good idea to take a look at the underlying technology that makes the board possible, in particular the chipset. AMD are a relative newcomer to the multi-processor arena with AMD CPU's traditionally used in uni-processor systems and it's only recently with the launch of the AMD 760MP and the chipset we are covering today, the 760MPX that AMD have offered a multi processor chipset for use with their CPU's.

Chipset support for multi processor systems is one thing but the CPU also needs to have certain features present before it can be used with a supporting chipset. To take one of these features as an example where the x86 architecture is concerned, there are a number of interrupt request lines (IRQ's) present in the system managed by the CPU. Hardware attached to the host bus that the CPU is connected to can raise interrupts on these IRQ lines and the CPU responds to the request. Simplified, this is how modern x86 systems work. The hardware, a graphics card for example, raises an interrupt on an IRQ line to signal to the CPU that it is ready to use the bus and send or recieve data (or both!) on the bus and the interrupt tells the CPU to manage that request.

This is fine with a single CPU when one CPU manages the single set of IRQ lines in the system and there isn't any complication (well, none that concerns us!). However when you add more processors to the system things get interesting. In the case of 2 CPU systems like we are looking at here, 2 CPU's have to manage one set of IRQ lines and therefore coordinate their operation. For example, say we have a graphics card sitting on IRQ15 and it raises an interrupt, what CPU should handle the request?

Special logic on the CPU called the IO APIC is mainly responsible for managing all the extra complication that arises from running more than one processor. When the machine boots, the BIOS is responsible for initialising the APIC logic on the CPU amongst other things. The operating system upon loading must also be able to work properly with 2 CPU's including managing the IRQ lines in software since the drivers in the operating system tell the hardware to raise an interrupt.

It's these added complications that give rise to processing overheads and are the reason why running more than one processor doesn't simply double performance. For each extra CPU added to an x86 system there needs to be extra management overhead for that CPU. This is the reason why some multi processor systems don't scale very well since the underlying architecture for the processors experiences the law of dimishing returns where the performance gained from adding a CPU is wiped out by the management overhead for it.

So we know that adding a processor to a system can be beneficial but there are trade-offs. It's the job of the managing chipset, in this case the 760MPX, to keep these overheads to a minimum and make sure that running a second CPU is worth the cost and effort. The actual mechanics of a multi processor system have been greatly simplified here and we could devote entire articles just to the intricacies of multi processor operation.

So let's take a look at the chipset and see if it does things right. It is AMD's flagship multi processor chipset so they can't afford to get it wrong.

The AMD 760MPX Chipset

Before we dive head first into the MPX version of the chipset, it's worth noting that there's a previous version of the chipset called the 760MP. The difference is in the southbridge and when there's a difference to highlight when we cross that bridge (pun intended? you decide!) we'll discuss it a bit further.

First off, lets take a look at a diagram of the chipset before we talk about things further.



Being a usual chipset design we have both north and south bridges. Lets take a look at the spec of both.

AMD 762 System Controller

• Two 266 MHz point-to-point AMD system buses, providing uniprocessor or two-way symmetric multiprocessor capability
• PC2100 DDR (Double Data Rate) Memory Controller with support for up to 4 GB of memory space (supports four Registered DIMM slots)
• AGP-4X Interface (supporting 1X and 2X modes)
• Dual Mode PCI 2.2-Compliant PCI Bus Interface
  • 66-MHz clock with 32-bit and 64-bit data path support (supports up to two PCI slots)
  • 33-MHz clock with 32-bit and 64-bit data path support (supports up to seven PCI devices)
• A 949-pin Ceramic Column Grid Array (CCGA) package
• 2.5 V Core

AMD 768 Peripheral Bus Controller

• Host (primary) PCI bus utilizing a 66MHz/32-bit interface (PCI 2.2 Compliant)
• Secondary 33MHz/32-bit PCI bus interface (PCI 2.2 Compliant), including PCI bus arbiter with support for up to eight external devices
• AC ‘97 Soft Audio Controller
• UDMA 33/66/100 compatible EIDE bus master controller:
• OHCI-based USB host
• Extensive ACPI-compliant Power Management logic:
• Privacy/security logic, including ROM access control
• Thirty-two General Purpose I/O (GPIO) pins (Many pins are multiplexed with other hard-wired functions.)
• Legacy-AT Compatible Logic:
  • Interrupt Controller (8259-based)
  • Programmable Interval Timer (8254-based)
  • DMA Controller (for LPC bus)
  • Legacy Ports
• Real-Time Clock (RTC):
• I/O APIC Controller
• Support for Distributed DMA and serial IRQ protocols
• SMBus controller with one SMBus port
• Random Number Generator
• A 492-pin BGA package; 26x26 BGA grid; 35x35 millimeters square
• Both 2.5-volt core and 3.3-volt output drivers; 5-volt tolerant input buffers