SK hynix has shared the first detailed description of a DDR5 DRAM chip. The firm showed off block diagrams and technical data slides at the International Solid State Circuits Conference in San Francisco earlier this week. DDR5 will offer double the bandwidth and density of DDR4 with improved channel efficiency.
We noted that SK hynix claimed to be the first chipmaker to develop DDR5 DRAM chips that met JEDEC standards back in Nov 2018. However, an EETimes report from the floor of the ISSCC reminds us that the DDR5 standard hasn't yet been set in stone by JEDEC, though it was supposed to have been finalised by the end of last year.
At the SK hynix presentation on Wednesday, chip designer Dongkyun Kim presented a white paper on a hynix 16Gb 6.4Gbs per-pin SDRAM chip that runs at 1.1V and measures 76.22mm2. The chip is fabricated in a 1ynm, 4-metal DRAM process, reports the EETimes. In his presentation Kim described various technical challenges that had been overcome, and how the SK hynix design team addressed them.
SK hynix factory expansion
In other recent SK hynix news, the firm is said to be spending $107 billion building four memory chip factories. The fabrication facilities will be located on a 4.5 million square metre site south of Seoul, with work commencing from 2022. Additionally, two existing SK hynix plants will be upgraded with a total of $49 billion in investment over the next decade, reports Fudzilla.
SK hynix hopes to address the demand for next gen memory in markets such as 5G, AI, and automated cars. Moreover, it hopes to be able to fend-off competition from Chinese chipmakers.
