Contract chipmaker TSMC has announced a new manufacturing process which has been dubbed N4P. Despite the name, like N4, this is a tweaked version of the N5 process technology. TSMC describes N4P as a "performance-focused enhancement of the 5-nanometer technology platform," and it says it can deliver improvements across the board – with regard to performance, efficiency, and density.
Pondering over the naming/family to start with, there have been five 5-nanometer processes introduced by TSMC thus far. It started with N5, which branched with offshoots to N5P and N5HPC. Then there was N4, which has been improved to deliver the new N4P.
Talking of performance comparisons and so on, TSMC says that the new N4P can offer "up to 11 per cent more performance than the N5 process," but when compared to N4, it is only a 6 per cent uplift. Other comparisons given only the new process vs N5, the N4P being 22 per cent more energy efficient with a six per cent increase in transistor density.
An underlying quality of N4P which may make it more successful/popular is that it also offers decreased complexity, with wafer cycle time cut, as it requires fewer masks. Of course, machine time is money, so this is a worthwhile improvement.
Lastly, N4P is said to be well-supported by TSMC’s comprehensive design ecosystem for silicon IP and Electronic Design Automation (EDA). Current customers can easily migrate from other 5-nanometer platforms, for faster and more power-efficient product refreshes with minimal effort.
Expect the first TSMC N4P tape-outs in H2 next year, with product launches around the same time as N3 (offering full node scaling compared to N5) debuts in 2023, with N4P representing value yet still a very modern solution.
