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AMD provides more 3D stacking info at Hot Chips 33

by Mark Tyson on 23 August 2021, 10:11

Tags: AMD (NYSE:AMD)

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Back at Computex in June, AMD ended its keynote address with a very interesting segment where it introduced a Ryzen 9 5900X CPU prototype with added 3D V-Cache. We learnt that this prototype was the result of AMD's first practical implementation of 3D chip stacking technology. The firm targeted the CPU cache for this modification, as it was clear it would provide immediate benefits to multiple workloads.

Slides shared at Computex showed that the 3D V-Cache enhanced prototype delivered 15 per cent faster gaming on average thanks to the massive bandwidth boost that stacking a 64MB 7nm SRAM onto each CCD using TSVs provided. AMD CEO Dr Lisa Su said the first high-end Ryzen processors using 3D V-Cache would enter mass production in Q4 this year.

At Hot Chips 33, AMD has provided some more background about its use of 3D packaging technology in upcoming processors. ComputerBase has published a write-up and a bountiful selection of presentation slides from AMD's presentation. Above, you can see that the TSV connections used by AMD for its 3D V-Cache connection are much denser than previous/rival technologies offer.

AMD focuses its comparisons on micro-bump 3D inter-chip connectivity which is far coarser (15x less dense), requires 3x greater interconnect power, and suffers from poorer capacitance and inductance characteristics.

Above you can see AMD is boasting of a '9u pitch' – which is much denser than micro bumps, or even Intel's Foveros Omni technology with a 36u pitch. However, in 2023 Intel is going to start creating Foveros Direct chips with <10u pitch.

AMD is also working closely with partner TSMC on more advanced and complex 3D stacking technologies. It makes it clear, though, that while modular design is the way forward, not all types of chips benefit from the same 3D packaging strategies. As the slide above explains, an optimal choice must be based on PPAC (power, performance, area and cost).

AMD AM5 platform leak

Documents that have leaked as a result of the recent Gigabyte hack attack have precipitated a few tech articles in recent days. A block diagram of the AM5 socket/chipset was put under the spotlight by TechPowerUp on Friday. It shows that of the platform will support dual-channel DDR5, but will be limited to PCIe 4.0.

Specifically, AM5 platforms will support 28 PCI-Express Gen 4 lanes. "16 of these are allocated toward PCI-Express discrete graphics, 4 toward a CPU-attached M.2 NVMe slot, another 4 lanes toward a discrete USB4 controller, and the remaining 4 lanes as chipset-bus," says TPU.

AMD moved to PCIe 4.0 over a year ahead of Intel with its Rocket Lake desktop processors, so it is interesting to see AMD cede PCIe 5.0 leadership to Intel. Intel has already confirmed that its Alder Lake-S motherboards will support DDR4 or DDR5, depending on the board you buy. The upcoming Intel desktop platform is also going to support up to 16 PCIe 5 lanes and a number of PCIe 4/3 lanes.

Another advance for AM5 that we can see in the block diagram is the provision of two 20Gbps USB 3.2 ports.



HEXUS Forums :: 10 Comments

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4x4.0 lanes for the USB 4 controller means you can have either one full speed 40gbps USB4 socket or two USB4 sockets operating at a shared speed maxing out at a theoretical top end of 64gbps, that's not bad. Obviously if it were PCIe 5.0 it would be 40gbps for both but I don't think AMD is losing out not going to 5.0 on the desktop (yet) and that's because it's not the same like the jump between 3.0 and 4.0. On 3.0 we were starting to see strain on all resources around the system as storage, GPU and other add-ins were all starting to consume quite a lot of bandwidth. With 4.0 we're not seeing that yet unless you are stocking your system up chock full of 4.0 SSDs and even then the difference between a 3.0 and 4.0 SSD can be “measured” in a human term but we're not really stressing 4.0 speeds yet so 5.0 speeds aren't observably going to much of a difference yet.

Also, 4.0 SSD controllers are still going through a substantial amount of iterative improvements and the cooling needed for higher end 4.0 SSDs will likely make it even harder for 5.0 SSDs to operate in the same way, we might see “mid range” 5.0 SSDs needing stronger cooling than their 4.0 “mid range” previous gen counterparts.

I suspect AMD didn't go for 4.0 this time because of the above and also because the signal doublers and resignalers (can't remember the term, the hardware you use to keep signal strength and quality over a distance) were a PITA for 4.0, 5.0 is only going to make it harder again. So we could see a flip back from AMD mobos being more expensive initially on release than the intel counterparts to being cheaper because of the opt for 4.0 compatibility.

But are we going to see again when AMD moves to PCIe 5.0 where the 4.0 AM5 boards could “theoretically” run at 5.0 speeds but AMD decides to lock it out. I actually agreed with AMDs lockout because people will enable the functionality, potentially have a poor experience with the board and then blame AMD/board manufacturer for an experience that was never meant to happen in the first place (the leaked BIOS was just testing and verification IIRC). I wanted them to allow it but have the BIOS display a full screen 10 second warning saying “your board is not specced for 4.0, yes it may be able to run it but if it doesn't work very well or breaks, it's on you for trying it out”

We'll see if Intels utilisation of 5.0 does them any favours but last I heard in July, Intels board partners were going through the ringer with 5.0.
PCIe 4.0 versus 5.0 is all about bragging rights at this moment in the tech cycle. PCIe 4.0 has enough bandwidth to contain the current, and near future peripherals.
3 or 4 years down the line….that may change.
In the general consumer market that is.
ohmaheid
PCIe 4.0 versus 5.0 is all about bragging rights at this moment in the tech cycle. PCIe 4.0 has enough bandwidth to contain the current, and near future peripherals.
3 or 4 years down the line….that may change.

Agreed!
Tabbykatze
….and that's because it's not the same like the jump between 3.0 and 4.0. On 3.0 we were starting to see strain on all resources around the system as storage…
I thought, incorrectly it seems as i can't find any info, that 5.0 was a more drastic change than 3 - 4. I could've sworn that i read that 5.0 needed physical changes like having a repeater/booster/retimers and much stricter isolation of the physical traces on the board.

The chances are I'm misremembering but on the off chance I'm not going to 5.0 seems like it maybe an unneeded extra cost.