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TSMC officially reveals its 4nm manufacturing process

by Mark Tyson on 10 June 2020, 10:10

Tags: TSMC, AMD (NYSE:AMD)

Quick Link: HEXUS.net/qael66

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TSMC has surprised semiconductor industry watchers with the announcement of its N4 node. This 4nm manufacturing process was not pre-announced or inked into any roadmaps. Obviously it will bridge the company's N5 and N3 nodes, but specifically TSMC Chairman Mark Liu told the EE Times that "N4 is an evolution from N5". The EE Times says that it had already heard industry sourced whispers concerning N4, a few days earlier.

The purpose of N5 is to deliver further refinement beyond TSMC's N5P. The plan looks similar to how TSMC slotted N6 into its lineup of offerings, as a refinement of N7P. That node provided an upgraded version of the best process TSMC had at the time, for silicon with improved performance and power consumption, and with designs remaining compatible. This allowed customers to migrate with minimal costs.

According to the plans revealed at TSMC's shareholder meeting, we will see the advancement of TSMC's manufacturing nodes as follows: N5 is live and the first products will arrive in Q4 2020, N5P will launch in 2022, and N4 will enter mass production in 2023. Meanwhile, N3 trial production will begin in H1 2021, and TSMC is accelerating its N2 process development.

All these manoeuvres, especially the node proliferation, will help TSMC to fend off the challenge from Samsung. The EE Times notes that Samsung may start production using its 3nm node as early as 2020. As for the headlining N4 node, "We're already in business negotiations with customers on N4," said TSMC's Chairman, Mark Liu.

In related news TSMC has confirmed that it is ceasing production of Huawei HiSilicon chips, to avoid US trade issues. A Chinese language report shared by Twitter's Retired Engineer indicates that AMD will step in to hoover up the vacant capacity.



HEXUS Forums :: 4 Comments

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Samsung claims 0.65x the area for 3nm compared to their 7nm so the numbers are purely fluff. If it was real, 0.65x would have been achieved with a 5.5nm process.

4nm in this case is similar to TSMC's 12nm, which is a modification of their 14nm, and is akin to Intel's plusses. Even 14nm is not a full shrink of 10nm. 14nm vs 28nm is more like 2.5x rather than 4x, and its similar for 7nm vs 14nm.

One “generation” focuses on transistor density(like TSMC 20nm, and 10nm did) and the other “generation” focuses on performance(like TSMC 14nm, and 7nm).

So if it looks like we're progressing faster than ever, we're not. Pre-28nm each true shrink brought both full density and performance gains.
Not really.. the Node size is referenced to the size a single transistor can be made, there is more than transistors in a CPU die capacitors/diodes/inductors/fuses. then there is required EMR distancing think of it as social distancing in in a CPU so one side of a given circuit does not pick up electrical signals from another and cause interference. so real life scaling does not follow the Nm node size that a transistor can be size wise.
PMMEASURES
Not really.. the Node size is referenced to the size a single transistor can be made, there is more than transistors in a CPU die capacitors/diodes/inductors/fuses. then there is required EMR distancing think of it as social distancing in in a CPU so one side of a given circuit does not pick up electrical signals from another and cause interference. so real life scaling does not follow the Nm node size that a transistor can be size wise.

Node size hasn't directly correlated with transistor size for ages - it's all branding these days, there's no 7 nm features in 7 nm chips
Xlucine
PMMEASURES
Not really.. the Node size is referenced to the size a single transistor can be made, there is more than transistors in a CPU die capacitors/diodes/inductors/fuses. then there is required EMR distancing think of it as social distancing in in a CPU so one side of a given circuit does not pick up electrical signals from another and cause interference. so real life scaling does not follow the Nm node size that a transistor can be size wise.

Indeed, in a round about way that is what I was implying, essentially its the etch/cut size you can have a transistor at the size but you also have to have connecting traces to ..so bye bye to anything that could resemble the node size.