Intel has shared some photos and slides showing off images and further details of its first shipping DG1 discrete graphics card. The publicity materials, sent to HEXUS by Intel this afternoon, show Intel's first dGPU for client computing in the form as it has now shipped to ISVs worldwide. However, welcome as the images and presentation slides are, they don't provide a great deal of information on the technical side of things.
As you will likely know already if you have been following the progress of Intel's DG1, there will be a single Xe architecture and it will scale all the way from ultra-mobile to exascale. Spanning this divide you will find products based upon Xe LP, Xe HP and Xe HPC GPUs. What we are seeing here is definitely on one of the lower rungs as it, as shown, doesn't feature any additional power connection - it is sub 75W.
Intel says that as an integrated GPU as part of Tiger Lake, Xe will deliver a "massive leap in graphics performance," and most tech commentators reckon it will do so by leveraging 96 EUs within the TGL SoC. In a statement accompanying the DG1 pictures and slides, Intel added that TGL will also deliver "double digit CPU performance gains," compared to Ice Lake.
The DG1 graphics card isn't just about Intel providing a 3D acceleration solution, it is also said to include "powerful media and display engines," and offer acceleration to both gamers and content creators - as well as being power efficient. Intel's shipping DG1 will enable developers to get ready for both this kind of graphics card - as well as upcoming TGL CPUs (and beyond).
The images of the card that is sampling to ISVs show a design which is pleasingly aerodynamic looking but minimal in a way too. The compact single fan card looks like it uses a cast alloy shroud and there is a stylish matt backplate too, with 'Xe' in gloss. This double slot card for developers appears to feature a quartet of full sized DP ports on its double slot bracket.
One last snippet from Intel concerns Xe-HPC. It says that these particular GPUs will additionally leverage "a new data parallel matrix engine, support for variable vector widths, a new scalable memory fabric, Xe link, and a new caching architecture called RAMBO Cache".
