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Purported AMD Epyc Genoa info points to 96C/192T chip

by Mark Tyson on 1 March 2021, 13:11

Tags: AMD (NYSE:AMD)

Quick Link: HEXUS.net/qaeqa2

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Roughly within a year AMD plans to launch its fourth gen Epyc processors (Genoa), according to official roadmaps shared previously. AMD has yet to release the third gen Epyc processors (Milan), but did take time out at CES in January to provide a demo of a 2P system easily trouncing a contemporary Intel system in WRF – a popular climate modelling app.

So what advances are going to be delivered by Genoa? As you can see above the official roadmap shows that Genoa will move to utilising AMD's Zen 4 processor cores, and it will be fabricated at 5nm. These are the major changes it has shared regarding its continuous improvement of its server platform. Of course there is more to it that this, and Twitter's ExecutableFix reckons he has added quite a lot of meat to the bones that we are certain of.

Key features of Genoa include the following according to the Twitter source:

  • 96-cores (192 threads)
  • 12-channel DDR5-5200
  • 128 PCIe gen 5.0 lanes (160 for 2P systems)
  • 320W TDP (configurable TDP to 400W)
  • SP5 (LGA-6096) socket

The above specs list was added to with a to-scale mock up of Genoa based upon the Rome processor. You can see that SP5 is squarer than its predecessor, and it should have 2002 extra pins compared to the current gen Epyc processors (LGA-4094). In the image below you can see the central I/O die is flanked by 12 chiplets, rather than eight, and this is how AMD expands the core count with Genoa. With each chiplet capable of packing eight Zen 4 cores that means the max core count of a Genoa processor will be 96C/192T.

Speaking of major changes, it is thought that the memory bus width will be 50 per cent wider and serviced by the 12-channel DDR5 memory interface, supporting DDR5-5333. PCIe gen 5.0 will double the bandwidth over the current PCIe gen 4.0. Last but not least, AMD is expected to be upgrading the I/O die to a newer process tech (possible 7nm) to rein in its size and improve its efficiency.

Genoa should be revealed / demoed at CES 2022 and released a year after Milan turns up. It is expected to compete against the Intel Xeon Sapphire Rapids architecture which similarly features DDR5 and PCIe gen 5.0 support.

Update: A purported AMD Eypc Genoa slide that surfaced on ChipHell says that the Zen 4 cores which will feature in this processor supports AVX3-512 and BFLOAT16 instructions. As always, sprinkle some salt on info from these sources.

Sources: ExecutableFix, VideoCardz (2), TechPowerUp



HEXUS Forums :: 16 Comments

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Daum :rockon:
Ah, this explains why Intel is finally allowing AVX-512 in desktop parts with Rocket Lake. It's unlikely AMD is fusing it off for desktop parts.

I just don't understand why we need several iterations of vector extensions instead of implementing variable-length vectors, Cray style. Less silicon area wasted, less issues with hot spots etc. The trouble with not owning the instruction set is that AMD has to repeat Intel's poor engineering practices to remain attractive.
96-cores (192 threads)
12-channel DDR5-5200
128 PCIe gen 5.0 lanes (160 for 2P systems)
320W TDP (configurable TDP to 400W)

This is just absolutely nuts, especially the 160 gen 5.0 lanes for 2P systems…that's over 600GB/S (or over 5tbps) of PCIe bandwidth.

Also, the power consumption is crazy, the Zen 3 were 64/128 at 280W giving around 4.5W per core whereas these new Genoa chips will be 320W over 96/192 which is around 3.4W per core! Even upping to the cTDP of 400W that's still 4.2W per core. That 5nm die shrink is working some serious magic.

On top of that, DDR5 at those speeds is absolutely needed, on a lighter touch when linus encountered the storage speed issue he explained quite well that the total PCIe bandwidth was almost all of the DDR4 bandwidth of the CPU.

Oh man, I can't wait to see these announced, demoed then tested, these are Ker-razy!

The only thing left for Intel after AMD adds AVX3 and BFLOAT16 support is NVDIMM support, hopefully AMD will be bringing something like that in.
Tabbykatze
Also, the power consumption is crazy, the Zen 3 were 64/128 at 280W giving around 4.5W per core whereas these new Genoa chips will be 320W over 96/192 which is around 3.4W per core! Even upping to the cTDP of 400W that's still 4.2W per core. That 5nm die shrink is working some serious magic..
Anand's 3990x review measured 3.0w/core at maximum load: 200w for the cores and 80w for the IO and IF, so there's an obvious place to make real efficiency gains without touching the CCXs. DDR5 might be lower power, PCIe5 probably isn't. Lots of variables at work.

Hard to say how much of an net efficiency gain there is without the rated frequencies.
hubber hubber…far too costly for most of us though.

It does make you think what could happen with next gen ryzen, could we potentially end up getting more than 16c/32t at the top end, ddr5 already gives the potential to double the ram capacity and adds ecc….

I wouldn't be shocked to see ryzen and threadripper merge into one platform.


Maybe this lack of stock is a good thing because the next version looks like it might be taking things up another notch (assuming next ryzen supports ddr5 etc)