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AMD set to release 32-core Ryzen Threadripper CPU

by Tarinder Sandhu on 6 June 2018, 04:14

Tags: AMD (NYSE:AMD)

Quick Link: HEXUS.net/qadufr

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AMD CEO, Dr Lisa Su, kicked off the annual AMD Computex press conference with the stat that more than five million Ryzen shipments have been made in just over a year since launch in March last year. That's good going.

Radeon RX Vega for the foreseeable future

As expected, there were no hard-and-fast updates for Radeon GPUs, meaning that the current Vega architectuere will headline consumer graphics for the remainder of 2018. That said, there was official mention of a Radeon RX Vega 56 Nano card manufactured in conjunction with PowerColor.

Looking towards the future, AMD showcased the incumbent Vega architecture running on 7nm silicon. No frequencies or other salient details were provided, but expect a small speed hike and reduced power consumption.

It is reasonable to assume, therefore, that next-generation Navi is still a ways off from consumer debut. Reading between the lines, we shouldn't expect it to see it for at least a year. This is likely the reason why rival Nvidia has been dragging its heels for its own next-generation consumer Volta architecture.

Ryzen Threadripper set to be bigger, faster

On to the meat of the conference, detailing soon-to-be-available products, Jim Anderson, head of the computing and graphics group, announced that AMD is releasing second-generation Ryzen Threadripper CPUs.

The present 1950X tops out at 16 cores and 32 threads that run at a peak 4GHz. Intel has just announced a 28-core jobbie destined for release later this year. Trumping both is the second-generation Ryzen Threadripper. Based on the 12nm Zen+ architecture and enhanced Precision Boost feature present on the new Ryzens, the standout feature is provision for 32 cores and 64 threads.

Encompassing four Ryzen dies connected via Infinity Fabric, it's pretty much a top-spec Epyc in consumer form. AMD showed the 32-core Threadripper finishing the Blender rather quickly, and you can expect it to be close to twice as fast as first-gen models, depending upon peak speed.

Getting to this size means upping the TDP from 180W to 250W, most likely. Still running on the X399 platform, expect to see revised motherboards from the select few manufacturers that explicitly support the supposed higher power draw.

In related news, Lisa Su mentioned that AMD has socket-compatible 7nm 'Zen 2' Epyc silicon in the labs and it's working 'really nicely'. Interesting times.

Presentation starts at 14m 15s



HEXUS Forums :: 34 Comments

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If Threadripper socket is only quad channel memory, I wonder if you only get 1 memory channel per die to balance things or if they leave 2 dies without any ram access so that lightly threaded work gets full memory width.
DanceswithUnix
If Threadripper socket is only quad channel memory, I wonder if you only get 1 memory channel per die to balance things or if they leave 2 dies without any ram access so that lightly threaded work gets full memory width.

Is the socket quad-channel only, though? If the DIMM slots are each wired directly to the socket then the CPU could potentially address all 8 as separate channels. Unless I'm misunderstanding how multiple DIMMs per channel are typically wired, that is.

EDIT! Nevermind, just checked the specs. Definitely quad-channel only.
DanceswithUnix
If Threadripper socket is only quad channel memory, I wonder if you only get 1 memory channel per die to balance things or if they leave 2 dies without any ram access so that lightly threaded work gets full memory width.

Technically speaking what we think of as the cores (four of them per CCX) don't communicate directly with the ram (or any external I/O), any off CCX data gets sent to the CCM whose job it is to place that data onto the SDF, it then gets taken off the SDF by a UMC and it's the UMC that communicates with the RAM, i guess you could get a bottleneck what with eight CCM's trying to feed four UMC's, I've not done the maths. :eek:
Corky34
Technically speaking what we think of as the cores (four of them per CCX) don't communicate directly with the ram (or any external I/O), any off CCX data gets sent to the CCM whose job it is to place that data onto the SDF, it then gets taken off the SDF by a UMC and it's the UMC that communicates with the RAM, i guess you could get a bottleneck what with eight CCM's trying to feed four UMC's, I've not done the maths. :eek:

The problem is things slow down when you go off chip, so if a core wants memory that is on another die then that request has to go off die to the memory controller on the other die. Going across a carrier in a package is way better than going socket to socket across a PCB, but there will still be a cost despite the best efforts of the ram prefetchers.

I'm guessing AMD already did the maths, which is why Epyc has 8 ram channels for 4 dies, normal Ryzen has 2 channels for 1 die.
Now you've got me confused, if a core wants to access data located within the local memory of another core on another CCX it would go via the CCM's, the memory controllers are not part of the dies, as in the four cores that make up a CCX can only talk directly to either one of the other three core (and their associated local memory (L1, 2, 3) or they can talk to that CCX's CCM.

Because ZEN was designed as a SoC the actual cores are pretty dumb as IF deals with all the communication that happens outside each group of four cores, including the memory controllers (UMC's) and any I/O request, if a core want's memory that's on another die it depends where that other die is, if it's within the same CCX it does it directly, if it's anywhere else a request is made to that CCX's CCM and the CCM places the request on the SDF for either another CCM or a UMC to take it off.

Basically the cores themselves don't have direct access to the DDR memory controllers (the UMC's) or even another CCX's CCM.