INTEL DEVELOPER FORUM, SAN FRANCISCO, Feb. 19, 2004 – As the world moves toward digital technology and vast amounts of new digital data are created, the converged computing and communications industry will need to make significant changes to the underlying “architecture” of its products and applications to improve the way people use data.

In a speech today at the Intel Developer Forum, Intel Senior Vice President and CTO Pat Gelsinger said computing performance in the future will be defined by innovative architectural capabilities in addition to speed, to realize the full potential of digital technology.

“Our society is creating massive amounts of complex data as the world continues to go digital, but it doesn’t have the capability to enjoy the full potential of this rich resource,” said Gelsinger. “There is a critical need for scalable, adaptable and programmable computing architectures that have the capability to recognize, mine and synthesize all of this digital data.”

For future computers to be more helpful, they will need to excel at three key abilities: the ability to recognize data patterns and models of interest to a specific user or application; the ability to “mine” large amounts of real-world data for these patterns; and the ability to analyze, or synthesize, large sets of data. These capabilities require more memory, processing power, bandwidth and storage, and will drive the need to change the basic architectural design of computing and communications devices.



New Architectural Approach for the “Era of Tera”

Gelsinger said Intel is enabling the move into the era of tera–scale computing by developing architectures that will enable computing and communication devices in the future to do the tasks that only today’s supercomputers are capable of handling.

“As Intel quickly approaches billion-transistor processors, we are aggressively developing innovative ways to use the added transistors by applying new architectural approaches that will ultimately result in much more useful computers.” He added that this will be done through architectures that can scale and adapt to their computing environments.

Gelsinger described some of the innovations that Intel is currently developing to make architectures scalable, including “helper-threading,” a technology that increases single-thread performance by intelligently executing parallel tasks on a single processor as needed. Another example of the ability to allow architectures to scale in order handle more and more complex tasks simultaneously is the integration of multiple processing cores into one processor.

Intel also is researching new technologies that will make these new architectures more adaptable to multiple environments, applications and users. For example, Gelsinger described how Intel researchers are developing a reconfigurable radio architecture for future chips that will enable devices to communicate over various networks, whether it be 802.11a, b or g, Bluetooth or other wireless technologies.

Architectural innovations such as these, combined with the continued increase in clock speed and in the number of transistors packed on to a single chip, will ultimately determine computing performance in the future.