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Microchip SMC 1000 8x25G enables 4x bandwidth for CPUs

by Mark Tyson on 29 August 2019, 13:11

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Arizona-based embedded control solutions company Microchip Technology Inc., a leading provider of microcontroller, analogue, FPGA, connectivity and power management semiconductors, has entered the memory infrastructure market. Its pioneering product is the SMC 1000 8x25G serial memory controller for high-performance data centre computing. The headlining quality of the SMC 1000 8x25G is that it enables high memory bandwidth required by next-generation CPUs and SoCs - up to 4x bandwidth - to alleviate the bandwidth bottleneck between CPU and RAM, with obvious benefits for AI and machine learning.

Microchip's serial memory controller is designed to address the gap that has opened up between the advance in CPU processor core counts and the average memory bandwidth available. "As the number of processing cores within CPUs has risen, the average memory bandwidth available to each processing core has decreased because CPU and SoC devices cannot scale the number of parallel DDR interfaces on a single chip to meet the needs of the increasing core count," asserts the tech firm.

To address the above concerns, Microchip's SMC 1000 8x25G interfaces to the CPU via 8-bit Open Memory Interface (OMI)-compliant 25Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. It explains that "the result is a significant reduction in the required number of host CPU or SoC pins per DDR4 memory channel, allowing for more memory channels and increasing the memory bandwidth available." In promoting its SMC 1000 8x25G, Microchip makes the case for OMI support which unlocks the memory protocol type/rate support with its media-independent OMI interface.

Perhaps you haven't heard of Microchip before, but it is partnered by some semiconductor tech giants. IBM, for example has partnered with Microchip to enable the strategic decision for POWER processor memory interfaces to utilise OMI standard interfaces for increased bandwidth. AMD and Google are also championing the OMI standard. Moreover, SMART Modular, Micron and Samsung Electronics are building multiple pin-efficient 84-pin DDIMMs with capacities ranging from 16GB to 256GB, conforming to the draft JEDEC DDR5 standard DDIMM form factor - and leveraging the SMC 1000 8x25G.

Source: Microchip press release, via EE Times.

HEXUS Forums :: 6 Comments

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Extra bandwidth?

Are you calling my band fat? Cheeky sods.
Puzzle as independence - where possibility of placing a puzzle is determined by his neighbors. The guys in marketing don't care or I am missing the clu?
The biggest winner here is AMD.
The biggest winner here is AMD.

Will be if they leverage this and many cores at a decent price, say in the new threadrippers
IBM have just moved to this, if AMD can leverage this properly, they may bring competition to P9 and P10 processors in the small socket ranges.