Press Release
Cadence Solution Enables Design of Single-Chip Wi-Fi for Consumer-Networking ProductsBracknell, UK, June 26, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Atheros Communications, Inc. used the Cadence® Encounter® Timing System for power signoff and Encounter RTL Compiler with global synthesis and physical layout estimation (PLE), to design the new Atheros AR9001 series of 802.11n chipsets. The AR9001 offers Atheros customers a wide range of price, performance and form factors, enabling fast penetration of the growing 802.11n market.
The Encounter Timing System is the most complete and integrated electrical signoff environment for faster optimization, debug and final verification for timing and signal integrity with power – a key requirement for Atheros and other leading design companies. With the Encounter Timing System, Atheros' engineers were able to gain time to market and achieve significantly increased productivity from having a common electrical view of their design throughout the flow, and a robust debug environment for rapid diagnosis of multi-dimensional and interdependent timing-closure issues. The same signoff-quality analysis is also used throughout their entire Cadence SoC Encounter™ RTL-to-GDSII system, thereby preventing unnecessary front-to-back iterations to reconcile timing mismatches, and enabling fast design closure.
Time to market is extremely critical for wireless consumer chips and the AR9001 made it more challenging with its increased integration and performance targets. The consistency of timing and signal integrity views, from implementation through final Encounter Timing System signoff, significantly accelerated the AR9001 design closure, and enabled Atheros to meet an aggressive tapeout schedule.
"Encounter Timing System is an integral part of the tapeout success of our AR9001 system-on-chip solution, which combines a wireless network processor and a BB/MAC in a single Wi-Fi chip," said Steve Padnos, Methodology Architect at Atheros. "Encounter Timing System in conjunction with Cadence Encounter RTL Compiler with global synthesis and physical layout estimation helped us achieve the industry's highest performance, dual-concurrent router design setting a new 802.11n performance benchmark. The performance of Encounter Timing System and the ease-of-migration made our adoption very easy. "
"With the Cadence Encounter Timing System, Atheros enhanced the development process of their latest AR9001 802.11n networking solutions," said Eric Filseth, corporate vice president, IC Digital Marketing at Cadence. "As this case shows, Encounter Timing System enables companies such as Atheros and their customers to realize significant benefits and savings through productivity and quality gains, as well as improvements to design optimization and overall project time."
Encounter Timing System and Encounter RTL Compiler are components of Cadence Encounter digital IC design platform and Cadence Logic Design Team Solution. Encounter Timing System is available in L and XL offerings; Encounter® RTL Compiler is available in L, XL, and GXL.
