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Toshiba announces 4-bit-per-cell QLC 3D BiCS flash memory

by Mark Tyson on 29 June 2017, 13:01

Tags: Toshiba (TYO:6502)

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Toshiba has announced that it is the first company to surpass a flash storage density milestone. Thanks to its development of 4-bit-per-cell, quadruple-level cell (QLC) 3D flash memory it has enabled a 768Gb (96GB) die capacity. For comparison its 3-bit-per-cell, triple-level cell (TLC) 3D flash topped out at 512Gb.

According to Toshiba its new technology helps it to achieve "the world's largest die capacity." Furthermore, it enables a 1.5TB device with a 16-die stacked architecture in a single package - again an industry first. Toshiba says that the challenge of reliably utilising QLC technology in 3D flash memory has been met by a combination of advanced circuit design and its leading 3D flash memory process technology.

"There will always be demand for compelling storage solutions that bring higher densities and produce a favourable cost/performance equation – our QLC technology falls squarely into that sweet spot," said the SVP of TAEC's memory business unit, Scott Nelson. "History has proven us right in the past when it comes to our visionary flash memory roadmap, and we fully expect QLC BiCS FLASH to continue our industry-leading track record."

The new flash memory will be used in diverse applications. QLC will help solve challenges facing data centres thanks to its lower power consumption and reduced footprint. Other targeted markets will include; enterprise and consumer SSDs, tablets and memory cards. It will be interesting to see any cost savings to consumers delivered by this higher density memory technology.

Toshiba has already shipped out QLC flash memory to SSD and SSD controller vendors earlier this month and they will be testing and evaluating it. Samples will be showcased at the 2017 Flash Memory Summit, from 7-10th August in Santa Clara, California.

In other flash memory news from Toshiba today, it announced that it had developed a prototype sample of 96-layer BiCS Flash three-dimensional (3D) flash memory with a stacked structure, with 3-bit-per-cell (triple-level cell, TLC) technology. It hopes in the future to apply its 96-layer process technology to QLC flash.

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