INTEL DESCRIBES LOW POWER, HIGH PERFORMANCE
FUTURE FOR PROCESSOR TECHNOLOGY
SAN JOSE, Calif, Oct. 15, 2001 - Intel Corporation today outlined new
processor and system design trends that will improve the overall computing
experience of users in the future. These include optimizing chip power
consumption and embracing new "parallel" processor design techniques.
Justin Rattner, Intel Fellow and director of the company's Microprocessor
Research Lab, opened the Microprocessor Forum here by saying that power
efficient designs are ushering-in a new era of "ultra dense" servers,
longer-lasting mobile PCs and more stylish and easy-to-use desktop PCs.
These technologies are emerging, he said, because designers are now
balancing power with performance when designing new products.
"The art of system design has changed," Rattner said. "As first
described at
last February's International Solid State Circuits Conference, Intel is now
prioritizing power consumption, reliability, functionality and connectivity
with speed. We're designing for the total computing experience, and that's
bringing new innovations to the table."
Rattner also said that Intel is leading the chip industry into a new era of
"thread level parallelism," where single processors are starting to
manage
data as if two real processors were present, which improves throughput and
system response time. Intel's future Hyper-Threading technology, based on a
thread-level design, is due in the Intel® Xeon(tm) processor for servers in
the first half of 2002. Intel's advanced design philosophy also has the
company on track to deliver multi-core, multi-threaded processors within the
next few years.
Additional Intel Microprocessor Forum Presentations
In subsequent addresses at the forum, Intel provided future details on
mobile, enterprise and communications technologies.
* Bob Jackson, principal engineer of the Intel Mobile
Platforms Group, described upcoming mobile Intel® Pentium® 4 processors,
saying that they will include special low power mobile technologies such as
enhanced SpeedStep technology and Deeper Sleep alert states for extended
battery life. He also discussed the "Banias" design for mobile
processors
due in 2003, saying that it will be able to turn off parts of the processor
that are not being used to save power and will bundle instructions for
faster execution.
* Intel Fellow Glenn Hinton provided an architectural update
on Hyper-Threading technology, saying that it "threads" data
instructions in
parallel streams by duplicating architectural registers within the processor
circuitry. John Shen, director of Intel's Microarchitecture Research Lab,
co-presented with Hinton and provided additional details on multi-threading
processor design.
* Separately, Intel announced a new technology that will
enable the company to deliver the industry's first fully programmable
network processors capable of performing at wire speeds exceeding 10
gigabits per second. Intel Fellow Matt Adiletta will further discuss the
technology in a presentation on Thursday.
* On Tuesday, Dr. Dileep Bhandarkar, director of Intel's
Enterprise Architecture Labs, will disclose a new processor code-named
"Nocona," a future member of the Xeon processor server family due in
2003.
He also said that the Xeon processor for servers is expected to reach 1.6
GHz or above in the first half of 2002, and that upcoming 64-bit
McKinley-based systems are expected to deliver an integer performance
increase of up to 1.7 times greater than today's Intel® Itanium(tm)-based
systems.
Intel, the world's largest chip maker, is also a leading manufacturer of
computer, networking and communications products. Additional information
about Intel is available at www.intel.com/pressroom.
*Intel, Pentium, Xeon and Itanium are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other
countries.
