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Review: Intel's 915P and 925X w/ LGA775, DDR-II and PCI-Express

by Ryszard Sommefeldt on 19 June 2004, 00:00

Tags: Intel (NASDAQ:INTC)

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DDR-II

I'll save talk on how DDR-II works since I've covered it already in a separate article. However, here's a choice section from that article, that directly relates to the DDR-II modules supplied with the press kit.

The signalling voltage for DDR memory, as laid out by JEDEC, is 2.5V. As we all know, running closer to 2.8V is the norm these days, especially with high performance memory, be it DDR400 speeds and very low latency, or DDR500 speeds and higher latency.

The signalling voltage for DDR-II is 1.8V. Using similar principles to those that we apply to CPUs, lower signalling voltage allows for higher clock frequencies. Lower voltage means less time needed for it to swing between no voltage, the signalling voltage, and then back again. Less voltage should also manifest itself in less heat and power consumption. Given that 4GB of DDR400 can draw 40W during a read, saving power with a lower voltage requirement will benefit everyone.

Latencies, specifically access latencies, where the DRAM is instructed to give up the goods onto the I/O pins, are expected to run to CAS-4 or CAS-5, especially in higher speed parts. As the LC article mentions, we gave up those kinds of access latencies back when we moved away from PC100 SDR SDRAM. tRAS also looks to be 8 cycles at the very minimum, given DRAM specifications from Samsung. We're used to tRAS being 8 cycles when running DDR500 speeds with current DDR, but it's common knowledge that low tRAS latencies are key to extracting maximum memory bandwidth performance on current memory controllers. Certain memory access patterns, random access mainly, will surely hurt when done on DDR-II modules, compared to DDR.


The DDR-II modules supplied with the press kit are Micron MT16HTF6464AG-53EB2 DIMMs, 512MB per DIMM, running at 533MHz with latencies of 4-4-4-12 (CL-Trp-Trcd-Tras). With low latency DDR-I DIMMs just released by Corsair, running at 2-2-2-5 @ 400MHz, and some DDR-I DIMMs running at 2.5-4-4-8 @ 550MHz, the latencies of the initial DDR-II DIMMs are rather high, compared to what we're currently used to.

We'll see how that impacts performance later.

Operating voltage for the supplied DIMMs is 1.8V, as JEDEC lay out in the official DDR-II specification. Here are a few photographs showing the modules and comparing them, size and pin wise, to a DDR-I module.

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