AMD Athlon 64 FX-62
Spec first, based on the data on the previous page, then pictures.| Specification | AMD Athlon 64 FX-62 |
|---|---|
| L1 cache per core | 64KiB data, 64KiB instruction |
| Clock frequency and Socket | 2800MHz, Socket AM2 |
| L2 cache per core | 1MiB |
| System Link | HyperTransport, 1 link, 2000MTs/sec, 1000MHz |
| Memory Controller | Dual-channel, DDR2-800, 128-bit |
| Process technology and fab | 90nm SOI, Fab30 Dresden |
| Transistor count and die size | 227.4M, 230mm², 1MiB per core |
| TDPmax, ICCmax, Voltage range | 125W, 90A, 1.40V |
ADAFX62IAA6CS is coincidentally my online banking password. Our ACBYF stepping example was packaged near the end of January this year. The rear of the chip shows you all 940 pins (I counted them, thrice, just to make sure AMD aren't scamming us out of a ground pin or two since you know what Dave Everitt, European Products and Platforms Manager at AMD is like when it comes to stealing). I jest, Dave, I jest!.
Sliding into AMD's new socket, it ticks over at 2,800,000,000,000 cycles per second, which is a lot, especially for the pair of 386SX cores AMD use to implement FX-62. Sorry, rev. F K8 cores.
We know performance of FX-60 is strong on Socket 939 -- indeed it's strong enough for us to call it the fastest x86 CPU yet sold in the consumer space at the time of writing -- so the big question is how does FX-62 advance that on AM2 via more megahurtz and its new memory controller.
TDPmax is up versus FX-60 (110W) at 125W, but it's low enough for the PIB cooler for FX-60 to cool the FX-62 without a problem. Of course, the CPU support's AMD's own x86-64/AMD64 instruction set architecture, regular 32-bit x86, and all three SSE instruction sets.
Effectively a pair of FX-57s (that single-core FX ran at 2800MHz, too, and still performs amazingly) on the same chip package, sharing an integrated memory controller and HyperTransport link to the rest of the system.
So just four and a bit months after the release of FX-60, we have Socket AM2 and FX-62. The performance of new versus old, and new versus old at old's clock speeds are what'll be most interesting to uncover, to see how the new memory controller affects performance.
I'll answer that in time, after a good look at the platform that'll host our performance evaluation.
