Specifications and analysis
CPU Specifications in detail
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Intel® Celeron 2.0GHz (20x100FSB (Quad-pumped))
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Intel® NetBurst™ Micro-architecture
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0.13 micron manufacturing process
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8kb of L1 data cache, 12kb of L1 trace execution cache
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128kb of L2 advanced transfer cache
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Copper interconnects
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100FSB, Quad-pumped to 400MHz
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1.525v operating voltage
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Integrated heat spreader
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S478 microPGA form factor
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52.8w heat output (68c throttling temperature)
A question of cache
Although based on the Northwood core, there have to be differences between the premium and budget processors. The Pentium 4 Northwood features 512kb of on-board L2 cache. The 2GHz Celeron features 128kb, and both caches work at full processor speed. L2 cache can be thought of as on-board CPU memory.
The CPU stores the most frequently used information in its L1 cache. Here is where it communicates with the information at the fastest possible rate. Due to factors of cost, L1 cache is usually limited to a very small size: 8k for both the Northwood and Celeron CPUs. L2 cache sits a little further away but on the same slab of silicon. If the information requested by the CPU isn't in L1 cache, it tries the L2 cache.
Naturally, the larger the L2 cache, the more information the CPU can keep in there at any one time. Modern CPUs try to clump data together, so if, for instance, you're dealing with pieces of data that are closely related (i.e bits of data that will most likely be used in succession on a repeating basis), the CPU would preferably like to load as much of it as possible into the L1 and L2 caches. This will allow it to access the data from cache instead of system memory when it's called for again. That's why the 512kb Northwood does a better job with, say, gaming than the outgoing Willamette (256kb).
The Northwood-based Celeron with only 128kb of L2 cache is, somewhat obviously, going to be handicapped by the lack of L2 cache storage. If the code you're working with is larger than 128kb and going to be used on a repeating basis, the Celeron will have to keep refilling the relatively low cache time and time again. However, if code is non-repeating, then a relatively low cache won't impact upon performance so much, as there's little to be gained from keeping the non-repeating code on die. It all depends upon the application you're working with. Large repeating data sets and a small cache is a recipe for poor performance. The trouble is that a cache miss scenario is all to easy to envisage with only 128kb of L2 cache.
400FSB
The Pentium 4 has moved on to a 533FSB (133FSB, quad pumped). The quad-pumped nature of the Pentium 4 dictates that satiating memory bandwidth is vital. At 133FSB, it can use up to 4.26GB/s of bandwidth. Intel have decided to keep the 2GHz Celeron at 400FSB (100FSB quad pumped). Probably in a move to make it as compatible as possible, it does somewhat diminish its performance potential. There's more to this as you'll find out later.
Voltage
The die reduction has allowed Intel to drop the operating voltages from 1.75v to 1.525v. We've seen just how well some of the Northwoods overclock, and the newest stepping seem to be even better. Overclocking this CPU should provide us with some interesting results.
In basic summary, the 2GHz Celeron can be considered to be a handicapped Pentium 4 Northwood CPU in most respects. It has the same basic architecture, but it suffers from only having a 128kb L2 cache: 25% of that specified on the Pentium 4. Further, limiting it to 400FSB (quad pumped) negates some of the benefits that may arise from having 4.26GB/s of bandwidth on offer (133FSB). On the upside, it's relatively cheap, is wonderfully compatible via the aforementioned 100FSB, and should overclock like a bat out of Hell considering it's a 0.13u CPU based on the very latest C1 stepping.
