A new memory-controller
Integrated tri-channel DDR3 memory controllerIntel's previous Core microarchitecture carried over the Pentium 4's front-side bus (FSB) design that connected the system memory to the processor, via a memory-controller hub on the northbridge of the supporting chipset. The inherent problem here centred around how the lack of memory bandwidth - a crucial determinant of overall performance - disadvantaged the processor, yielding only 12.8GB/s on a top-speed 1,600MHz FSB, with less bandwidth available on slower-speed models.
What we saw was that the chipset's dual-channel controller's throughput was effectively wasted by the narrow FSB. AMD, on the other hand, with its integrated dual-channel memory-controller, did better here, harnessing greater throughput and therefore able to keep pace with Core 2 in memory-related applications, particularly in the server/workstation space.
Intel has remedied this flaw by introducing a tri-channel controller that's housed directly on the CPU, thereby getting rid of the archaic FSB for good. Now, just like AMD, requested information is loaded straight from system RAM into the CPU, ready to be processed. The three-channel design means that when compared to Core 2 a) more bandwidth is available and b) that more of it can be used.
Initially supporting three 64-bit DDR3-only channels at 1,066MHz speeds and using a number of aggressive prefetching techniques, Core i7 will, theoretically, be able to pump around 25.6GB/s - via a NUMA (non-uniform memory access) - from system memory to CPU, which is a far cry from the 10.6GB/s available on current Core 2s with a 1,333MHz FSB.
We surmise that Intel has done this to keep present and future Core i7 cores sated with all-important bandwidth - a move that AMD implemented some time ago.
