Instruction Set Architectures
At its base, an instruction set architecture is a set of processor instructions that separates the underlying hardware from the software that executes on it. The ISA defines a strict set of implemented processor instructions and an ISA implementation is the functional implementation of those on a processor.With the original x86 ISA specification, itself coming from models that IBM has used on its own mainframe systems back in the 1960's (indeed, every major architecture in use in computing today has a clearly defined ISA), Intel had created a set of processor instructions that would be implemented on all of its x86 processors.
So all processors that are x86 compatible must have silicon that allows correct execution of the instructions defined in the x86 ISA.
How do modern processors do that?
A modern processor doesn't implement each x86 instruction in silicon, rather a set of smaller instructions (microcode instructions) are used as the generic building blocks to perform the defined ISA instructions. Microcode instructions are then combined together to implement an ISA instruction, transparent to the software running on top that is compiled for that particular ISA.
It's this fact that gives processor manufacturers the ability to enhance performance of an ISA on subsequent processors they create, by optimising the underlying silicon and microcode instructions in such a way that code executes faster than before.
This also creates todays situation where all new processors based on an ISA must maintain backwards compatibility with code written for older implementations of that ISA. In terms that we can relate to, that means for example, Pentium 4's must run code written for 386's, despite a huge functional difference in the implementation of that ISA, they both implement the same ISA nonetheless.
This also brings us on to advances in the ISA, such as the move to 32-bit's (instructions, address space, addressable memory), or things like HyperThreading or PAE. As technology marches on, limitations in an original ISA spec designed decades ago have quickly become apparent. The need for applications to address more than 4GB of memory became a reality in the recent past, therefore PAE was implemented on top of the existing x86 ISA to allow 36-bit addressable memory blocks for applications that needed more than the 4GB that 32-bit gives you.
HyperThreading is an addition to Intel's NetBurst implementation of the x86 ISA, but it was imperative and absolutely necessary that HT processors still run code that was designed for CPU's without HT.
So the ISA itself, the cornerstone of a hardware and software platform, is necessarily extended during the course of its life to encompass needed enhancements that software requires, while still maintaining backward compatibility with older implementations.
But since it's impossible to build a flawless ISA that can be extensible in any way, providing for all advances in computing that are required, there comes a time when a rethink of how things are done on that ISA becomes necessary. The ISA becomes a limiting factor, rather than a means of enabling technology to progress.
Intel hit upon that recently with their clean break from x86 with IA-64, a 64-bit ISA developed with Hewlett Packard, that implements a 64-bit platform, but without any explicit x86 compatibility at all. They decided that a clean break was the best way for them to provide 64-bit computing, something the enterprise had demanded for a long time.
AMD on the other hand decided not to follow suit. x86 implementers since their inception, following Intel again as a clone IA-64 producer wasn't an option that was feasible for AMD. But the shift to 64 bit computing was in progress and AMD had to do something to provide for that, otherwise they'd find themselves without a market in due course.
So they came up with x86-64, an extension to the x86 ISA that Intel were unwilling to do, but something that appears to be somewhat of a master stroke for AMD, given current market conditions.
The enterprise seems to clamour for a 64-bit x86 ISA that will run current code, while allowing them to develop their next generation of software that requires it. In the past, an application that required the benefits of 64-bit processors would require a port to a commodity UNIX, using often unfamiliar tools and running on very expensive hardware.
x86 and Windows is the most pervasive architecture in use in computing today, meaning implementation of applications that require 64-bit features, on cheap commodity hardware, using the tools they've been used to on x86 on non UNIX platforms in the past is a godsend. With Linux also a huge player in the 32-bit x86 enterprise space with massive investment from a huge range of companies, the ability to develop the next generation of applications on Windows and Linux, while continuing to run 32-bit x86 code faster than before, using existing tools, is what a lot of companies have been waiting for.
Full 64-bit operation (data, address space, memory address size) while maintaining the ability to run 32-bit x86 code faster than any existing 32-bit x86 implementations. Sounds good to me, let's take a closer look.
