AMD ATHLON64 FX-51 CPU
AMD present K7-series of processors has done it proud. The Athlon CPU first fought off the attentions of the Pentium III series of processors, it then had enough muscle to see of the stunted Pentium 4 Willamette and, more recently, a couple of core changes to the present 200FSB Barton has helped it keep up the heat on the new, improved Pentium 4 Northwood 200FSB CPUs. However, with Intel busy readying the replacement to the Northwood, in the shape of the prodigious Prescott core, which will encompass, amongst other things, a 90-nanometer manufacturing process, improved Hyper-Threading, 1 MB L2 cache and maybe an improved SIMD instruction set, AMD really does need to fight back with a vengeance.
The current K7-series is headed by the XP3200+, a Barton-based core with 64k L1 data cache, 64k L1 instruction cache and 512kb L2 exclusive cache, giving an impressive 640kb of usable on-die cache (note that the data in L2 is exclusive, i.e it isn't repeated in L1 data cache). More on-die cache partially negates the need to keep running to the far slower system memory each time more data is requested by the CPU. PC4000 memory may be fast for system RAM, but it is an order of magnitude slower than the CPU's speed.
As enthusiasts will no doubt tell you, the Barton core, for all its goodness, is close to hitting its architectural ceiling. A 10-stage integer and 15-stage floating-point pipeline is great for combatting the effects of cache misses, but it also limits the overall clock speed AMD can gain. AMD, with due recognition that Prescott was around the corner, and perhaps to design a CPU that may cover a few markets, including the server, workstation and consumer, with one stone, decided to effectively retire the K7-series as the performance champion. Something new had to come along that would serve AMD for the next couple of years.
Enter the Hammer and, more specifically, the Athlon64 FX-51.
Enhanced 32-bit x86 architecture being extended to 64-bit. 64-bit support with Linux and Microsoft OS's becoming fully ready to complement the CPU ?. On-die memory controllers with super-low latency access that'll undoubtedly boost performance in memory-intensive activities ?. More L2 cache for large dataset applications. Sounds too good to be true, doesn't it?. Read on.