vacancies advertise contact news tip The Vault
facebook rss twitter

Micron's GDDR6 offers twice the bandwidth of GDDR5

by Chris Elt on 14 December 2015, 12:01

Tags: Micron (NASDAQ:MU)

Quick Link: HEXUS.net/qacw2o

Add to My Vault: x

Micron will launch its GDDR6 memory next year, according to an exclusive report carried by Fudzilla. The new generation memory will offer twice the bandwidth of GDDR5 and "will be the company's answer to HBM". The development, launch schedule and some key specs of GDDR6 have been confirmed by the Director of Micron's global Graphics Memory Business, Kristopher Kido, says the source.

Looking at the important key performance specs of GDDR6, users will benefit from memory bandwidth of 10 to 14Gb/s. That compares very well, as much as doubling up, to the 7.0Gb/s of 4Gb GDDR5. The promised 8.0Gb/s data rate of 8Gb GDDR5 is also not coming close to reaching GDDR6.

Importantly for its adoption by the industry GDDR6 brings not just extra speed and bandwidth, but a component form factor which is similar to GDDR5. As Fudzilla reports, this will reduce "the burden and complexity of design and manufacturing," new graphics products using GDDR6.

Since HBM is still in short supply and HBM 2.0 in development GDDR6 could be a very worthwhile stopgap for the industry in the next year or so. Looking at 2016 we will have 14 and 16nm GPUs emerging and new fast memory technologies coming into play at the high end and perhaps lower down thanks to GDDR6.

HEXUS first reported on the leaked slides showing Micron's development of GDDR5X back in October (as in the example above). It appears that the magnitude of the improvements on offer (and the marketing department) has pushed for the adoption of the designation of GDDR6 for this new faster and higher bandwidth memory.



HEXUS Forums :: 22 Comments

Login with Forum Account

Don't have an account? Register today!
“the company's answer to HBM”

Seems somewhat hyperbolic, if you ask me: even at 14Gb/s on a 512b pathway it wouldn't quite double the bandwidth available from the Fury's HBM1 implementation, which means that a four-stack HBM2 implementation would still out-do the best a 512b GDDR6 implementation could offer, in a much smaller silicon area, and presumably also at lower power usage. Sounds more like a stop-gap while they try to work out what their actual answer to HBM is, if you ask me… ;)
I thought one of the main points of HBM was that it reduces the power consumption of the memory interfaces, because wiggling a pin faster doesn't come for free.

So unless power consumption is addressed somehow, and if it was I would expect this press release to be singing it from the rooftops so I assume it isn't, then this seems like a not so useful improvement.
DanceswithUnix
… unless power consumption is addressed somehow … this seems like a not so useful improvement.

AFAICT (and assuming this IS the same stuff as GDDR5X) the actual clock rate won't change, but the doubled pre-fetch will allow twice as much data to be transmitted per fetch? Which is curious, because I thought that was what GDDR5 already did to get the high data rates compared to GDDR3/GDDR4. Since it's targeting data rates that are double the existing GDDR5 range I assume that the clock and signalling rates will remain which means it won't consume (much) more power than a comparable GDDR5 implementation. Still a big chunk of the power budget going to driving the memory though; it definitely looks like more of a stop-gap measure than a forward-looking memory subsystem enhancement. I guess it might be useful for mid-range (128-bit) cards: if it's similar enough to GDDR5 we could start seeing GDDR5/GDDR6 cards instead of the existing GDDR3/GDDR5 ones….
Wiggling a lot of short pins at 1GHz will always beat wiggling long pins at 6GHz or whatever this runs at, this will only help designers smooth out any memory bottlenecks on a recycled mid-range GPU design. Or let them downsize on memory bus silicon area, to boost yields on the new processes. A die shrunk 295X2 with this to help keep up at 4k would probably embarrass a lot of top-end chips, and without any pricey interposer.
As the article says, this is clearly trying to take advantage of the low availability of HBM. I suspect anything below an R9 or GTX*70 will end up with this memory tech for pure volume capability.