Scaling down to ever-smaller manufacturing processes has enabled technology firms, in concert with enhancements to architecture, to improve performance of successive generations of chips without sacrificing energy consumption. Transistor-gate geometry is expressed in nanometers, with 16/14nm now being the preferred process for cutting-edge silicon used in mobile and desktop chips.
But time waits for no company, so system-on-chip (SoC) designers, whose chips are found in every mobile device, have been keen to extract the benefits accrued from using 10nm. For example, ARM, a world leader in IP designs for mobile processors, has previously announced a close collaboration with foundry partner TSMC on the 10nm FinFET node and inked a multi-year deal for silicon based on 7nm technology.
Today, ARM is announcing that its next-generation CPU IP for premium smartphones, codenamed Artemis, has taped out on TSMC's 10nm process at the back end of last year and is now at the silicon test-chip level. A test chip is a simplified version of an SoC that will go into production at a later point, though, importantly, it uses the same silicon for validation purposes.
This shrunken-down SoC, which includes a quad-core CPU and single-core Mali graphics, is useful to ARM because it shows what kind of power, performance and area characteristics can be applied to larger chips to be used by the company's partners from next year onwards in volume. It is usual for a fully-functional test chip to precede high-volume silicon by around six months.
What's arguably more interesting is the performance and power results obtained on the chip. Depending on where you look on the curve, with normalised power vs. normalised performance, there's over 10 per cent more perf or, more pertinent to those SoC guys who want to build energy-efficient SoCs, a considerable drop in power for the same level of performance as current 16nm FinFET, which, remember, is considered cutting edge for 2016.
And efficiency is very much key to how ARM views the next roster of mobile IP, be it CPU, graphics, display or interconnects. To that point, “efficiency is a primary guiding principle in SoC design for premium mobile applications due to increasing demands on device performance,” said Pete Hutton, executive vice president and president of product groups, ARM.
Back on to 10nm, the above graphic is somewhat unfair as it compares the incumbent Cortex-A72 processor on a mature 16nm FinFET+ process, optimised through ARM POP technology, to a fresh-out-of-the-factory, nascent 10nm process. We know this as the test chip uses iteration 0.5 of the physical design kit (PDK).
One can reasonably assume that the combination of natural process maturation and POP will lift the Artemis' frequencies to those matching, or even marginally beating, the Cortex-A72. How real-world SoC guys will actually clock in their silicon is a different matter. What is more telling is how the power consumption goes down through a combination of process and new architecture for Artermis.
Anyone with a passing interest in next-generation mobile performance should care about this slide because it tells us, indirectly, to expect the 10nm CPU cores to run no faster than what's commercially available now. Performance gains will come from architecture more than higher frequencies made possible by the smaller geometry.
A test chip is a harbinger of widespread SoC silicon by a matter of months. Appreciating that ARM has had it back from TSMC for what appears to a be a short while, and is now in the process of hardening it through its POP IP infrastructure, the next-gen mobile SoCs, powering premium hardware, may be closer than you think.
