APUlicious
AMD has previously announced such heterogeneous cores under the Fusion platform. APU is the physical manifestation of such thinking and will be coming to market sooner than you might think. Think of it as a system-on-a-chip and you won't go far wrong.
By their very nature, CPUs are excellent at processing code that has to be put through sequentially. The low-latency x86 architecture is fast but narrow, as even the latest processors run with 'only' four execution units in parallel. On the other hand, GPUs are much wider and can process masses of instructions on a parallel basis - perfect for data that can be spread around and fired through SIMD arrays. The Radeon HD 3870 has '320' stream processors, all capable of working on a variety of code concurrently. Such broadness effectively masks the bug-bear of GPUs: latency. GPUs have a far higher peak throughput, as measured in FLOPs, as well.
You'll always need a scalar architecture (CPU) for offload tasks, but an 80-core CPU doesn't make much sense to AMD, Hester noted. Rather, an APU can be architected for specific platforms - CPU-heavy for the workstation/server environment and GPU-heavy for the media-rich (and ever-so-parallelisable) desktop and mobile spaces. CPUs are fast enough to open your Word spreadsheet or Outlook but struggle when tasked with transcoding high-definition media, something that GPUs can thrive on if the application is coded for correctly.
The third possible accelerator within an APU would be a dedicated ASIC, where a fixed design is better-suited to the task at hand. Such an accelerator exists today in the form of AMD's UVD (Unified Video Decoder), which is reckoned to a more-efficient way - in terms of power and transistor budget - than having a GPU decode computationally-expensive high-def. content.
Announced in December 2007, such accelerator-specific thinking will be available in just over a year's time with the Swift APU that will fall under the Shrike platform, designed for laptops.
Integrating a 45nm AMD DDR3-supporting CPU and a GPU core on to the same die, it will have a dedicated UVD and PCI-Express bus right on the core. The building-block approach will let AMD add a further CPU or GPU core as it sees fit. Why have these requirements discrete when you don't have to? An all-in-one design saves on power but external interfaces mean that you can still run a discrete video card in higher-power notebooks.
The downsides to this elegant solution are design complexity - which'll increase as transistor-rich cores are added - and possible yield issues. AMD, though, already has a tried-and-trusted accelerated computing APU in the form of its Xileon SoC.
What we think
APUs make implicit sense where power is of primary concern. Hester
commented that a CPU-only architecture is dead, because why wouldn't
you integrate everything that's needed? We agree with this sentiment
and can see genuine advantages of such an APU approach, which'll reduce
power-draw and, hopefully, cost, too.
We're reasonably confident that APU thinking will spread to the desktop
environment as more and more users will offset pure power for a smaller
form-factor. There will always be a demand for multi-core CPUs and
high-power discrete graphics cards, of course, but APUs, where
technology is leveraged to meet the real needs of the average consumer,
seems to be a winner.
The question is whether AMD can fulfil easy-to-make PowerPoint promises and deliver compelling product, on time, and in quantity.
Look out for more exclusive coverage from HEXUS.net and HEXUS.tv on AMD's first European CTO Summit of 2008 in the coming hours and days, including why we think that, if AMD can execute on Hester's vision, then post its acquisition of ATI, AMD at least in itself, finally seems to be making Smarter Choices...
