Intel Xeon 51xx, Intel 5000X core logic and FB-DIMMsWe start with the CPUs themselves.
Intel Xeon 51xxXeon processors with a product sequence number starting 51 are Woodcrest-based, with 4MiB of shared L2 cache and either 1066MHz or 1333MHz (both effective rates) bus clocks, and up to 3GHz external frequency initially (the 5160 we're reviewing today).
TDP for the 3GHz model is 80W, while the rest of the range, right down to the slowest 1.6GHz 5110 is a 65W part, barring one low voltage model at 40W, called LV 5148 (2.33GHz, same as the 5140). Here's the list.
|Processor||Frequency||Socket||L2 cache||Bus speed||Virtualisation||EM64T||TDP|
|Xeon LV 5148||2.33GHz||LGA771||4MiB||1333MHz||Yes||Yes||40W|
Core-based as discussed, that's the first-run lineup to take on Opteron in the dual-processor server and workstation space. Each chip can work in tandem with another, which leads us on nicely to discussion about Xeon's departure from the shared bus.
We've commented in the past that Xeon's requirement to share the bus to the memory controller with other Xeons in the system is a barrier to higher performance when bound by the memory subsystem. The new Xeon CPUs don't have that limitation any more, each chip getting its own bus to the memory controller that it uses exclusively. Each core on the CPU shares that bus, of course, but it's a significant removal of a limitation long observed as something holding Xeon back.
At 1333MHz (333MHz quad sampled), that's just under 11GiB/sec, with bus bandwidth increasingly linearly with the number of CPUs in a system.
Intel 5000X core logicAlong with the new processors, Intel also have new core logic designed to host the chips and provide their connectivity to the rest of the system, including system memory.
The 5000-series of core logic is available in three flavours, with the X variation -- codenamed Greencreek -- for workstation platforms and thus the one we'll focus on here.
5000X provides a DDR2 memory controller that you populate with fully buffered DDR2 ECC registered DIMM modules, up to 333MHz (DDR2-667) in frequency and up to 64GiB in total system capacity on a DP system.
The use of fully buffered (FB) DIMMs means that, theoretically, memory bandwidth is increased and access latency is reduced, but at the penalty of power draw and heat increased brought on by the use of the buffer chip itself. Intel say about 5W extra per DIMM. Yowzers.
PCI Express (PCIe) is the interconnect of choice for the 5000X IC, with 16 lanes for graphics and 8 lanes for external I/O with other devices. It doesn't support any multi-GPU graphics teaming for performance reasons, but many mainboards providing 5000X will split the 16 lanes into 8 + 8 for dual board support.
The 5000X MCH is also a part of the Woodcrest CPU supporting virtualisation and EM64T, and when given Dempsey (another Netburst-based Xeon) to work with, it supports HyperThreading too.
It also supports the aforementioned dual discrete buses for the CPUs to ride on, just two of which are there for DP running. Most board vendors will pair the 5000X with a 6000PXH PCIc/PCIx controller, and the 6321ESB southbridge I/O processor which provides 6 SATA2 controllers with RAID5, 6 USB2.0 ports, 12 lanes of PCIe, a PCIx segment (64/133) and (if we're reading the spec sheet right), three GigE ports. Woohoo.
So a full-featured base platform that's largely equivalent, features wise, with what you get from i975X in the consumer space, bar the PCIx bits, higher bus rates and support for two CPUs rather than one.
FB-DIMMsA quick bit on the goodies that FB-DIMMs provide, before we move on to a look at a Greencreek + Woodcrest box in the flesh. The buffer chip isn't as dumb as you might think, and it does more than just data buffering. It's a processor in its own right, checking data integrity in both directions (memory location and memory address), after being instructed by the MCH, and its able to retry a memory operation in the event of something going wrong, until it's right, something that'd hard-stop a previous Xeon system.
The buffered nature of the device means that it can present data to the CPU faster than a typical access would take, since the data is already there on the chip waiting to be placed on the pins. That's where the lower latency and higher bandwidth come from, with the chip doing funky things with data prefetch and writing, to keep throughput high.
And not specifically related to FB-DIMMs themselves, but all FB-DIMM-supporting MCHs that we've seen from Intel also supports single-module failover and hot replacement (even on 5000X), without data loss or downtime. Sweet as!
SummarySo new Core-based Xeons at high bus speeds, with support for FB-DIMMs and a sweet-looking chipset, all ready to take on Opteron in some heavy-hitting performance testing. Should be easy to understand why the new Xeon platform improves on the old, both in CPU architecture and core logic implementation.
Let's look at a physical Woodcrest system, ably provided by the mighty Armari.