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IDF Spring 2005: Manufacturing Enhancements to CMOS Technology

by David Ross on 1 March 2005, 00:00

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Manufacturing Enhancements to CMOS Technology



Another Spring, another IDF, without doubt at this IDF we will be bashed about with Dual Core and Vanderpool technology, as well as Intel screaming at us about how well Itanium is doing. This is not forgetting about their vision of the digital home and office. However, pre-IDF Intel has held a number of briefings for the international press. The first of which was centered on the change in the manufacturing process – present and future.

One of Intels rules which was predicted by Gordon Moore is that of 'Moores law'; this law states the doubling of transistors within micro processors year-on-year. Over this time we have heard skeptical comments about this from various parties, yet Intel is still standing by a strong belief that this will remain the case for many years to come.

We have seen, with the reduction in the manufacturing process, the cost of transistors plummeting and this coupled with new technologies will hopefully enable Intel to keep CMOS technology alive and kicking for at least another 15 years.

In the presentation Intel looked back to 1994, where it was believed that 100 nanometers was the absolute limit for CMOS technology; and this would be a fundamental limit. The other limit was believed to be the cost of the transistors with the shrink from 250 nanometers to 100 nanometers.

Since 1994 there has been some changes to funding, for example, in 2000 the California Institute of Technology gave a grant of $500 to the national nanotechnology initiative. This initiative had key goals which were purely for research, in order to dispel some myths about the cost of producing silicon, namely the fabrication plants (of which Intel have several).

The cost of these plants is incredible, around a 3 billion dollar investment for a fab which is setup to build on 300nm wafers, a 200 nanometer wafer fab will cost around 2 billion dollars, yet the cost per volume is a lot higher; thus the 300 nanometer works out cheaper per chip produced. Intel will, in 2005 be producing significant volumes of the 65nanometre chips.

Whilst still working on the 300mm wafers the next major drop in the manufacturing process will be the introduction of 45nanometre chips in 2007 and a 32nanometres version by 2009; both of these will be on the 300mm wafer with the aim to migrate to a 450mm production line.

Another technology which Intel is heavily researching is that of the deployment of High-K; this is the increase in power which is passed through the transistors, aiming to give you higher current and lower voltage. This is the opposite of what ATi have deployed in Low-K, which aims to give you lower voltage for lower overall heat output (making it ideal for mobile solutions). High-K will also bring a lower amount of leakage with increased capacitance.

There are other options open to Intel and other manufacturers apart from just reducing the transistor size, one of which is called Strained Silicon. This process consists basically of stretching the silicon in order to spread out the electrons – this enables faster electron flow through the transistors. Look at it like a shopping center – if there are lots of people shopping they are densely packed, making it harder to get through, but if the isles were made wider (or in the case of the chip the silicon stretched) creating more room, then the shoppers can get from where they are to where they need to be quicker and easier. Electrons, like people, need space in which to move.

This sort of technology coupled with the 65nanometer process can give anything up to a 4x reduction in leakage, or the ability to increase the current without having such a big increase in leakage. There is already strained silicon technology being used on the Intel 90 nanometer manufacturing process and we will see that on all future processes. We will not see, however, the introduction of High-K until the introduction of the 45nanometre process. Intel will also couple this with the change to metal gate electrode rather than poly silicon at present. Of course, as with most future things, this is subject to change over time.

The is the main problem with using transistors is leakage and Intel have been spending a lot of time and money on the problem, looking for a solution. One such solution is a move to Tri-Gate transistors; these work by insulating the transistors to give lower leakage and voltage requirements. Of course at the moment there is no need for these but in the future we may well see the movement from the current Planar CMOS to Tri-Gate.

With these smaller transistors you also need the interconnects to work with them – so the introduction of low-K enables lower capacitance, thus allowing electrons to move faster between the transistors, increasing chip performance and reducing the power needed.

With the reduced manufacturing size there is a potential problem with the use of copper interconnecting wire, with smaller wire sizes increasing the amount of resistance which can occur. A long term solution will need to be found; and indeed Intel already have some in the form of Carbon nanotubes and nanowire. If Intel do choose to use the carbon nanowire it will enable them to have much more voltage running through the wire compared to copper. However we are unlikely to see this being used for 15 years or so and until we do Intel will have to keep the quality of the wires as high as possible.

There are other solutions which can be used which include the use of a 3D interconnect, which splits the lanes (copper wires) in half and flips them over – this way you get less resistance per lane. Some of the challenges which Intel will face with the deployment of nanowire how exactly to use them; for example if you pass certain voltages across them you can align the nanowire but in order to create a working circuit significant work is needed.

As with all of these enhancements Intel will have to work out which option is best for their future, and work on that more so. Since silicon is not going anywhere but has an 'in-built' limit of 1.6nm which is the distance between individual electrons.