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Some more details on Nehalem. 16-threaded monster showcased

by Tarinder Sandhu on 19 September 2007, 15:21

Tags: Intel (NASDAQ:INTC)

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Pat Gelsinger managed to cram in an impressive number of Intel buzzwords into once sentence yesterday. We're adamant that tick-tock, cadence, and ubiquitous received suitable oratory.



One a more serious note, Gelsinger also touched upon 45nm-based Nehalem, the code-name given to Intel's next-generation microarchitecture, to be launched next year and a natural successor the upcoming Core architecture-based Penryn.

He recapped on information already in the public domain, that is, Nehalem will feature an integrated memory controller (DDR3) and cores will communicate with each other via high-speed QuickPath interconnects, offering 3x the bandwidth of 'competing processors'. Front-side bus has been relegated to the doldrums, evidently. Select Nehalem SKUs will support integrated graphics, right on the die - a la AMD's Fusion.

We also know that the Nehalem, in its 'extreme' configuration, will be made available as an octo-core processor with SMT (Symmetric Multithreading) enabled, which brings the possibility of concurrently processing 16 threads from a single-socket CPU. A quad-core Nehalem packs in around 731M transistors, we found out, so we wonder at the count of the full-fat eight-core model. The architecture will be roped in to the server, desktop, and mobile market, in various configurations, as per recent multi-platform-wide strategy.

Demonstrating a couple of quad-core Nehalems chugging away at rendering, Jim Brayton, project manager for Nehalem, commented that the A0 silicon was just three weeks old. Nehalem or quad-CPU Tigerton? Who knows for sure!

Brayton was quick to comment that Westmere, the 32nm advancement to Nehalem, was coming along just nicely and scheduled to meet its 2009 deadline. We wonder what else he could have said, frankly.


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A quad-core Nehalem packs in around 731M transistors, we found out, so we wonder at the count of the full-fat eight-core model. The architecture will be roped in to the server, desktop, and mobile market, in various configurations, as per recent multi-platform-wide strategy.


Sounds to me like it would be an MCM, similar to Clovertown is now.

Hang a second die off an on package CSI link, get access to memory and other sockets through the first die (with a bit of a latency penalty).
Sounds to me like it would be an MCM, similar to Clovertown is now.

Hang a second die off an on package CSI link, get access to memory and other sockets through the first die (with a bit of a latency penalty).

Well, all the information out of IDF is that Nehalem in this incarnation, is a monolithic quad core... if you check around other sites, the diagram for this demo was a dual socket, hence 8 total cores. Since each core can crunch 2 threads, this gives a total count of 16, 8 physical cores and 8 logical cores (2 SMT recongized cores per physical core), so 16....

In essense it is a CSI link ... between two sockets, just like AMD's cHT link between two sockets...