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Intel to produce Cannonlake, Icelake, Tigerlake on 10nm node

by Mark Tyson on 25 January 2016, 10:01

Tags: Intel (NASDAQ:INTC), TSMC

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A report on financial orientated website The Motley Fool says that Intel is planning to launch three processor families manufactured on the 10nm process node. If true this will be the second time Intel has produced three processor families on the same node. On the current 14nm node Intel has made Broadwell, Skylake, and we learnt about six months ago that a 'stopgap product' called Kaby Lake would be released later in 2016.

The first Intel 10nm architecture processor will be Cannonlake and should arrive in H2 2017. We have heard about Cannonlake before and seen it mentioned on some roadmaps. Another interesting thing about Cannonlake is that it is expected to bring the first consumer processors that go beyond quad-core.

Following Cannonlake The Motley Fool writer has been tipped by sources that Intel will produce a 10nm chip called Icelake. Icelake will be launched in H2 2018. Then the final 10nm chip to be launched by Intel will follow a year later and be known as Tigerlake. That's Tigerlake launched in H2 2019. If all those plans fall in place we should be looking at Intel's first 7nm architecture processor launch in H2 2020.

Will Intel get back to producing two products per process node with 7nm? Of course it's too early to say but "If all goes well for the company, then 7-nanometer could be a two-product node, implying a transition to the 5-nanometer technology node by the second half of 2022. However, the source that I spoke to expressed significant doubts that Intel will be able to return to a two-years-per-technology cycle," reports The MotleyFool.

Keeping the above timescales in mind, Intel investors, like the Motley Fool reporter, are a little worried that Chipzilla could be overtaken by the likes of TSMC. "Taiwan Semi claims that it will go into high-volume manufacturing on its 10-nanometer technology (which should have slightly better density characteristics than Intel's 14-nanometer technology) in late 2016/early 2017." TSMC plans to begin mass production of its 7-nanometer node during H1 2018. This is very interesting for the competitive landscape, and don't forget that Samsung is galloping ahead with its semiconductor manufacturing plans giving Intel rivals even more options.



HEXUS Forums :: 21 Comments

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“ Another interesting thing about Cannonlake is that it is expected to bring the first consumer processors that go beyond quad-core., ”

If games and to be honest ANYTHING I use a PC for used more than 4 cores (most only use 2) then I would be all for this. As it stands however, forget more cores and give us more speed. We should have had 5Ghz chips outta the box ages ago, If I can clock a 3570k to 4.5ghz and it be stable for near 3 years now why on earth can't they just make them like that to start with :(
Plasmastorm
We should have had 5Ghz chips outta the box ages ago, If I can clock a 3570k to 4.5ghz and it be stable for near 3 years now why on earth can't they just make them like that to start with :(

Intel were racing towards higher and higher clock speeds with the NetBurst architecture. It was a terrible idea, in hindsight. The focus since then has been on efficiency - getting more done with less as opposed to getting it done by just plain old throwing more speed at it.

It's probably much easier from a manufacturing point of view to put out somewhat conservative clock speeds on chips. Sure, on a K-series processor you can push into the high 4.0 GHz range, but not every chip will do it that easily and some chips won't do it at all, so Intel can't (or won't) guarantee that kind of speed if there are going to be chips that can't handle it.
I'm fully expecting lots of 8/12 core 2ghz chips instead of 4 core 3.5ghz ones.

That is the way computers are going as they ran out of the clock speed dimension.
More cores, more efficient use of them and _faster memory_ would help.

The current memory clock nonclemature is as deceptive as cpu speeds.

Latencies (wait states) mean that higher clock speeds don't result in the delay from a memory request to data coming back being any shorter than a decade ago. DRAM may be cheap(*) but it's a major bottleneck in current architechture.

(*) Cheap being relative. The amount of effort spent making it run faster and the amount of silicon supporting those higher speeds without significant errors(**) means that the laws of diminishing returns have been in effect for quite a while.

(**) ECC is pretty much mandatory these days. I've seen more ECC events on ram in the last 5 years than the previous 2 decades.
Surely the answer to latency is to increase cache on the chip. Ram can't always increase in speed as it makes PCB designer more difficult.