22nm SoC incoming
Mark Bohr, Senior Fellow of Technology at Intel, discussed future architecture thinking at IDF 2012. You may know that Intel has two different processes for CPU and system-on-chip (SoC) processors. The firm has already launched 22nm CPUs under the Ivy Bridge range, and the underlying silicon is internally referred to as P1270. SoCs, meanwhile, use a different process variant, designed for low power and low-current leakage, and it is known as P1271. SoC-type chips are commonly found in smartphones and embedded systems.
22nm SoC silicon - P1271 - is ready for production, according to Bohr, and it is likely to be 'productised' in late-2013. Rumours reported previously on HEXUS indicate that the first iteration of this SoC will be called Valley View, based on the Silvermont Atom architecture. If true this would mean there's an 18-month lag between CPU and SoC products.
Intel currently uses a technique called immersion lithography for manufacturing chips. This works well but becomes problematic as processes become smaller. Looking further down the line, immersion lithography needs to be augmented by the double whammy of multiple patterning and multiple exposures at smaller nodes, which adds to the cost of manufacturing.
The next step in lithography is a technique called extreme ultraviolet (EUV), but Bohr commented that the necessary tools for cost-effective EUV manufacturing simply aren't ready. Intel has invested in ASML to speed-up this lithography transition, however. Intel will continue to use multiple-patterning immersion lithography until at least the 10nm node, said Bohr, and he hoped that EUV would come online soon after, which means the 2014-2015 timeframe.
Make mine a large wafer
Conveniently ignoring heck of a lot, manufacturing silicon using larger wafers is a good idea. Current chips are based on 300mm wafers and per-unit cost continues to drop as smaller-transistor, high-density nodes - such as 22nm and 14nm - are implemented. This is true even though the cost of tooling for node transitions is increasing from one generation to the next.
Intel designs and manufactures its own silicon. It would dearly love to move to 450mm wafers as soon as possible, meaning, over time, it shift to a lower cost curve. These 450mm wafers are not going to be available on the short-term horizon, according to Bohr, citing the lack of complete tools as the main obstacle to adoption. At a best guess, we can expect to see 450mm wafers in four to five years' time.
Intel is actively investigating the potential for 3D chip-stacking - putting chips on top of each other - where, say, memory is literally placed on top of the CPU through a technique called through-silicon via, with a sub-mm gap between the two components. The benefits of this approach include lower power consumption and higher bandwidth. Bohr commented that the main impediment of using chip-stacking rests with cooling high-performance chips and cost-effective production for low-power chips. It's largely inevitable that chip-stacking technology will be used in future processors, though the exact timeframe to adoption is unknown.
Bohr believes that Intel is 'years ahead' of the competition with respect to silicon manufacturing, especially with the recent introduction of 3D transistors and lead in process nodes.