Following on from yesterday's announcement that its 45nm production for K10-series Phenom processors is on track, we took a closer look at a wafer of 45nm wafer of 'Shanghai' cores.
Fresh out of Fab 36, the 45nm process packs in more than just a die shrink, however.
The four execution cores will be augmented by a total of 8MiB of on-chip cache that comprises of 2MiB of L2 and a further 6MiB of L3. That, then, is a tripling of L3 cache compared to the incumbent models.
Adding more cache decreases the need for the processor to traverse to slower system memory, speeding up general performance on a clock-for-clock basis when compared with 65nm Agena.
Adding more cache, as Intel knows only too well, increases the transistor count. The die space for Shanghai is around the same as the current Agena SKU, thanks to the space-saving benefits of the 45nm process.
Native quad-core support will be augmented by tri-core models that will be released in present 65nm flavours real soon. Tri-core will be achieved by either deliberately switching off a perfectly-functioning single core or, as AMD hopes, bringing to market silicon that didn't quite make the quad-core grade first time.
AMD has confirmed that 45nm CPUs will be available in H2 2008. What really needs to happen in the interim is healthy frequency scaling by the Phenom core, to better-compete with the higher-clocked and more-profitable Intel 45/65nm quad-core parts.
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