Building core logic
IntroHEXUS: Hey John, thanks for agreeing to chat to HEXUS for a while about core logic. Seems like we found the right guy to talk to!
John: No problem, what can I do for you?
HEXUS: Since you're an ASIC guy, mind if we talk silicon for a while?
John: Not at all, go ahead.
SB600HEXUS: Can we talk about SB600, your new upcoming southbridge product? I/O silicon, especially with Athlon 64 and Athlon FX, is often what'll define a mainboard for some people, since it sets out the base features. Can you tell us what's new and improved in SB600 compared to the current SB450?
John: Since I am not a member of our southbridge design team I can't give you an official answer. However, we do work very closely (northbridge and soutbridge teams) and can tell you that SB600 will deliver a wide variety of improvements to our current generation of products. We are focusing heavily on I/O performance since it can make or break the platform.
HEXUS: So we're talking new USB controller at the very least, since that's the main area of complaint with RS480 designs that use SB450?
John: To put that ‘issue’ into perspective, were talking about a few hundredths of a second slower than the most robust competitive product when transferring an MP3 file from a USB memory stick to a PC. But there will be improvements, for sure.
HEXUS: And are you updating A-Link bandwidth between the SB600 and whatever northbridge product it gets paired with?
John: A-link 2.0 is pretty much PCI Express so increasing bandwidth isn't all that difficult. However, bandwidth isn't the only important metric for good I/O performance. Latency is also very important. I can't tell you exactly what is planned, but both areas are being scrutinized and you can expect some improvements in these areas.
Designing core logic ASICsHEXUS: We've always wondered about how you go about designing and producing an ASIC, from a blank design to production silicon. It's something that rarely gets discussed so some stuff on that would be great. What kind of tools are you using at ATI to produce ASICs? Eric Demers on the GPU side has talked in the past, I forget where, about the move to Verilog from VHDL at ATI, as the software you'll use to design logic? Is that the case for your chips?
John: Yeah, we use Verilog exclusively inside of ATI now. We switched from VHDL a few years ago now, company wide, so the core logic design team will use Verilog now to design a new chip.
HEXUS: And after the Verilog is done and you've finished up testing in the simulator, maybe an IKOS?
John: Well, I can't comment on the simulator hardware we might use. *laughs*
HEXUS: *laughs* OK, so after you've brought it up in the simulator and you think it's just about there, you'll bring it up on test silicon first, using an FPGA? Oh, before you answer that if you can, just so our readers know, FPGA stands for field-programmable gate array and they're chips that you can use to test prototype chip designs before you send them off for full production. They often run only at a few KHz right?
John: Yeah, that's right, and we'll use FPGAs to prototype our silicon after we've done the bringup work in the simulator and with our CAD tools. So the FPGA will be faster than the simulator, but it's many times away from the performance of a production chip.
HEXUS: And you're using, what, Xylink FPGAs for that?
John: *laughs* Well, I can't answer that, but I can tell you we aren't using Xylinx hardware right now.
HEXUS: *laughs* Right, so Actel?
John: I really can't answer that but, *pauses*, well, there's not much outside of Xylinx we'd use *laughs*
Time from blank design to working siliconHEXUS: I've always wondered how long it takes you to design your silicon, from blank design to getting it onto a board. Can you talk about that, say with RS480 as an example?
John: Absolutely. So with RS480 that was a clean-sheet design from RS300 and RS350 right? So we're starting over with a brand new part that's implementing almost entirely new stuff. We went from supporting Intel CPUs to supporting AMD, so that's an entirely new bus for the CPU. We integrated a DX9 part whereas RS300 was DX8, so there's a brand new graphics core on there. We went from AGP to PCI Express, so a completely new graphics bus for discrete. And there's a new chip link in there, A-Link 2 I think we call it which is PCI Express again, so two PCIe interfaces on the chip. Pretty much all new.
HEXUS: Right, so we're thinking that based on that you've got an 18 month window, maybe two years from getting started on that product to the first boards we saw this year?
John: Haha, not at all. We brought RS480 up from scratch in just over 12 months. Took us a year.
HEXUS: Start to finish, first Verilog to production silicon, really 12 months?
John: Yeah, just a year. Pretty cool huh?
HEXUS: Indeed! Much quicker than we had an idea of.