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Intel's upcoming Nehalem is the new AMD Phenom

by Scott Bicheno on 17 March 2008, 19:00

Tags: Intel (NASDAQ:INTC)

Quick Link: HEXUS.net/qamas

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Bells and whistles

Stephen Smith, vice president and director, Digital Enterprise Group Operations at Intel, gave journalists a sneak preview of its latest processor microarchitecture, codenamed Nehalem.

Nehalem is the latest iteration of Intel’s ‘Tick-Tock’ product development strategy, in which it promises to deliver a new manufacturing process every odd year and the second generation microarchitecture based on it every subsequent even year.

So at the end of 2007 we had Penryn – the first 45nm processor (the Tick) – and now we have Nehalem – second generation 45nm microarchitecture (the Tock) – which is scheduled to go into production in Q4 ’08.

Nehalem is essentially basic Intel Core 2 microarchitecture with some important bells and whistles, many of which, it must be noted, are already present in equivalent form in AMD’s Phenom microarchitecture.

 

 

For example, Nehalem is a monolithic design that can be architected in two-, four- or eight-core models. Each core is allotted the same L1 cache as the incumbent Penryn - 64KiB, split equally between instructions and data cache.



Then there's per-core L2 cache, amounting to 256KiB, which is supplemented by an 8MiB L3 cache that's shared amongst all cores. Kind of remind you of a certain Phenom's architecture, right?

Another 'new' feature is the Quick Path Interconnect (QPI), which replaces the traditional Front-Side Bus (FSB), and there are also integrated memory controllers (IMC), which do away with the traditional MCH on present Intel chipsets.

Each of these features apparently delivers an up to six-times improvement on what’s currently being made. Kind of reminiscent of HyperTransport and the integrated memory controller on AMD's Athlon/Phenom CPUs, if you ask me.

Boosting bandwidth and reducing latency is a three-channel memory controller, based on presently-available DDR3.

Further Nehalem goodness is to be found within its parallelism. The architecture is able to process 128 micro-ops concurrently, compared to Core 2's 96 and Core's 64.