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Zen developers were given "total freedom," says AMD engineer

by Mark Tyson on 24 September 2015, 10:06

Tags: AMD (NYSE:AMD)

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In the wake of the news of legendary CPU architect Jim Keller leaving AMD last week, there was a lot of discussion about the upcoming highly anticipated Zen microprocessor. The success of this upcoming processor is vital for AMD as it battles its performance and business challenges. Zen is expected to be the foundation upon which AMD builds new ranges of processors from late 2016/2017 onwards and then refines for several years thereafter.

It seems that with Zen the AMD top management realised that it needed a complete break from any previous conceptions about how processors do their thing, and thus Zen has been built "from scratch" to be the best it can be.

An Austin, Texas newspaper recently published an interview with Suzanne Plummer, a veteran chip engineer who heads the Zen team, and has worked at AMD since 2002. Plummer had some interesting things to say to The Austin American Statesman about how Zen was developed; "It is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do," Plummer said. "It is a multi-year project with a really large team. It’s like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and (low) power consumption over the previous generation."

According to AMD's own presentation slides concerning Zen performance, the new generation processor cores will offer a 40 per cent performance improvement over its Excavator cores at the same clock speeds.

An analyst speaking to the Austin American Statesman summed up the pivotal chance AMD has with Zen; "Everything is riding on Zen," thought analyst Nathan Brookwood from Insight 64. "They are shooting for performance parity with where (arch-rival) Intel will be." If AMD doesn't make the grade it could be in serious trouble.



HEXUS Forums :: 39 Comments

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Just curious but in the first slide it mentions High-Bandwidth low latency cache system, is that possibly pointing towards HBM cache? Would HBM cache even been possible, or an advantage over traditional cache?
Corky34
Just curious but in the first slide it mentions High-Bandwidth low latency cache system, is that possibly pointing towards HBM cache? Would HBM cache even been possible, or an advantage over traditional cache?
HBM would make for a sort of next level cache (L4?) as it bridges gap between cache and system memory or could provide a specific cache to Gcards since HDM is really used for gcards currently. it's interesting to see how these techs may merge in the future.
Might be similar to the 128mb of L4/GPU ram on the Broadwell desktop parts.
Lets hope they develop an awesome chipset to go along with the amazing CPUs/APUs/GPUs coming next year!
Corky34
Just curious but in the first slide it mentions High-Bandwidth low latency cache system, is that possibly pointing towards HBM cache? Would HBM cache even been possible, or an advantage over traditional cache?

ValkyrieTsukiko
HBM would make for a sort of next level cache (L4?) as it bridges gap between cache and system memory or could provide a specific cache to Gcards since HDM is really used for gcards currently. it's interesting to see how these techs may merge in the future.

Gunbuster
Might be similar to the 128mb of L4/GPU ram on the Broadwell desktop parts.

Might be a play to or a requirement of the next generation of consoles too. So the PC version might not end up with a massive HBM cache but the console version might have a lot of ‘cache’ / embedded memory more for a powerful APU / all in one type solution.

Exciting if it really is a ground up design though (unless that's just marketing BS). Could really shake things up (fingers crossed). 40% more IPC is impressive but I wonder how that compares to the latest Intel chips.